Solving complex 3D packaging challenges
Since 1998, Amkor Technology has been a pioneer in developing and providing high volume, low-cost 3D packaging technologies. Our development through deployment approach transcends the range of applications and packaging platforms requiring 3D technology. Customers benefit from this approach as new 3D packaging solutions are more effectively qualified and ramped to high volume, at low cost, and across multiple factories.
Critical 3D platform technologies include:
- Design rulesand infrastructure for thinner, high-density substrate technologies
- Thinner die attach and die stacking processes
- High density and low loop wire bonding
- Pb-free and environmentally conscious green material sets
- Flip chipplus wire bond mixed technology stacking
- Turnkey die and package stacking assembly and test flows
Amkor’s die stacking technologies are widely deployed in high volume manufacturing across multiple factories and product lines. Next generation die stacking technology includes the ability to handle wafers and die thinned down to below 35 µm. It can be reliably stacked and interconnected with up to 16 active devices high, employing leading-edge die attach, die spacing,wire bond, and flip chip assembly capabilities.
Die stacking is also widely deployed in conventional leadframe-based packages includingQFP,MLF®, andSOPformats. Leveraging Amkor’s industry-leading infrastructure for high volume, low-cost leadframe production, system designations can achieve significant savings in printed circuit board real estate and overall cost.
Stacking of fully assembled and tested packages is an area where Amkor has provided significant innovation to overcome technical, business and logistics limitations associated with complex die stacks. Amkor’s advancedPackage-on-Package (PoP)packaging solutions include:
Package Stackable Very Thin Fine Pitch BGA (PSvfBGA)supporting single die, stacked die using wirebond or hybrid (FC plus wirebond) stacks and has been applied to Flip Chip (FC) applications to improve warpage control and package integrity through test and SMT handling.
Package Stackable Flip Chip Chip Scale Package (PSfcCSP)enables the use of an exposed die bottom package integrating the package stacking design features of PSvfBGA in a fcCSP assembly flow. PSfcCSP has a thin exposed FC die enabling fine pitch stacked interfaces at 0.5 mm pitch, which is a challenge in a center molded PSvfBGA structure.
Through Mold Via (TMV®)is our next generation PoP solution with interconnect vias through the mold cap. TMV technology provides a stable bottom package that enables use of thinner substrates with a larger die to package ratio. TMV enabled PoP can support single, stacked die or FC designs. This package is an ideal solution for emerging 0.4 mm pitch low power DDR2, DDR3 and follow on memory interface requirements. Additionally, TMV enables the stacked interface to scale with solder ball pitch densities to 0.3 mm pitch or below.
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