The broadest range of flip chip package solutions
on the market

Amkor is committed to being the leading provider of Flip Chip in Package (FCiP) technology. By partnering with proven industry leaders, Amkor has brought high volume flip chip packaging and assembly to the subcontract market.FCBGA, fcLBGA, fcLGA,FlipStack®CSP andfcCSPpackages are qualified and in production. Flip chip production capability exists in our Portugal, Philippines, Korea, Taiwan, and China factories.Wafer bumping, wafer level packaging (WLP) and flip chip packaging solutions are qualified in lead-free options.

Using flip chip interconnect offers many possible advantages to the user:

  • Reduced signal inductance– Because the interconnect is much shorter in length (0.1 mm vs. 1–5 mm), the inductance of the signal path is greatly reduced. This is a key factor in high-speed communication and switching devices
  • Reduced power/ground inductance– By using flip chip interconnect, power can be brought directly into the core of the die, rather than requiring rerouting to the edges. This greatly decreases the noise of the core power, improving the performance of the silicon
  • Si Integrated Heat Spreaders (IHS)– Si Integrated Heat Spreaders are available for fcCSP packages. As a result of robust thermal conductivity and ease of processing, Si is an effective alternative to Cu as a heat spreader material. Si Integrated Heat Spreaders can be embedded inside the mold while exposing its top surface to an external heat sink

  • Higher signal density– Rather than edge only, the entire surface of the die can be used for interconnect. This is similar to the comparison between QFP and BGA packages. Because flip chip can connect over the surface of the die, it can support larger numbers of interconnects on the same die size
  • Reduced package footprint– In some cases, total package size can be reduced using flip chip. This can be achieved by reducing the die to package edge requirements (since no extra space is required for wires) or by utilizing higher density substrate technology, which allows for reduced package pitch
  • Die shrink– For pad limited die (where size is determined by the edge space required for bond pads), size of the die can be reduced, saving silicon cost


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