Next generation bump technology for greater density, reliability and performance

Copper pillar bump enables finer pitches making it an excellent interconnect choice for applications such as transceivers, embedded/application processors, power management, baseband, ASICs and SOCs. This technology allows for smaller devices, reduces the number of substrate package layers and is ideal for devices that require some combination of fine pitch, RoHS/green compliance, low cost, and electromigration performance.

Copper pillar platform

  • Fine pitch CSP
  • Area array fine pitchFCBGA
  • µBump: F2F,TSV

Production status

  • +300M units shipped since 2010
  • Copper, lead-free and copper/Ni/lead-free
  • 14 nm in production

Package structure

  • Bare die CSP/PoP
  • Molded PoP/TMV®
  • TSV


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